There has been a conventional image processing apparatus that executes the blending process in which a superimposed portion of a source image of a lower layer is removed, the source image is divided into a divided image to calculate a division display address, and a source address is calculated according to the division display address to read the source image from an image memory (for example, refer to Patent Literature 1). In the image processing apparatus, the source image is divided into the divided image from which the superimposed portion of the source image of the lower layer is removed so that data of the source image overwritten and lost by a source image of an upper layer through the blending process is not read from the image memory. Through the above processing, a traffic to the memory is reduced to enable a reduction in the costs or electric power of the memory.
FIG. 18 is a diagram illustrating a configuration of the image processing apparatus in a conventional example disclosed in Patent Literature 1. Referring to FIG. 18, an attribute memory 1810 is a memory that stores attribute information including source addresses indicative of data areas of the respective source image data, display addresses indicative of areas on a display screen, and display priorities, which are data for forming the blended image. An image memory 1830 is a memory that stores source image data therein, and a display screen 1820 is a display screen that blends the source images together. A rendering circuit 1840 reads the source image stored in the image memory 1830 on the basis of the attribute information stored in the attribute memory 1810, forms the blended image, and outputs the image as the display screen.
The rendering circuit 1840 forms the display image shown in the display screen 1820 from source images att1, att2, att3, and att4 stored in the image memory 1830. The display priorities become lower in the stated order of att1, att2, att3, and att4, and att1 is a source image located in the lowest layer, and att4 is a source image located in the highest layer. In the display screen 1820, respective pixel areas 1821, 1822, and 1823 of shaded parts are area in which the source images can be superimposed on each other through the blending process. The rendering circuit 1840 executes the blending process on a line basis of the display screen.
FIG. 19 is a diagram illustrating an image division process of an area between v1 and v2 of the display screen 1820. Through a source image division process 1850 between v1 and v2, in the area between v1 and v2 of the display screen 1820, the source image is divided into the divided images. In the source image division process 1850 between v1 and v2, rectangular areas become the divided images obtained by dividing the respective source images of att1, att2, att3, and att4, and the source image att1 becomes the divided image in which areas in an h2-h3 interval and an h4-h5 interval corresponding to the pixel areas 1821 and 1822 of the superimposed areas are removed. After the divided image has been generated, the display address of the generated divided image is calculated, the source address is calculated from the calculated display address to read the source image from the image memory 1830, and the source image is output to the memory that stores data of the display screen 1820.
Citation List
Patent Literature
Patent Literature 1: JP-A-2002-229554